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VDD=VDDQ= 1.8V +/- 0.1V

• Fully differential clock inputs operation
• Source synchronous-data transaction aligned to bidirectional data strobe
• Internal eight bank operations with single pulsed RAS
• Differential Data Strobe
• All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
• Programmable CAS latency 3, 4, 5 and 6 supported
• Programmable additive latency 0, 1, 2, 3, 4 and 5 supported
• BL switch on the fly
• tRAS lockout supported
• 8banks
• Programmable burst length 4/8 with both nibble sequential and interleave mode
• Auto refresh and self-refresh supported
• JEDEC standard 60ball FBGA(x4/x8), 84ball FBGA(x16)
• Full strength driver option controlled by EMR
• 8K refresh cycles /64ms
• Dynamic On Die Termination supported
• Off Chip Driver Impedance Adjustment supported
• Read Data Strobe supported (x8 only)
• Operating Temperature: 0 to +85 °C
• Storage Temperature: -55 to +100 °C
• Self-Refresh High Temperature Entry
• ROHS compliant